The present invention relates to improving the data extraction technique for use in a communications system or recording system.
Data extraction is one of various signal-processing techniques applicable to communications and recording systems. The data extraction technique is exploited to accurately extract data either from received data that has been transmitted through a communications channel or from a signal that has been read out from another component in a given system.
As shown in FIG. 16, a data extracting circuit 100 for a communications system extracts a train of read clock pulses, which are synchronized with received data, from the received data, and also outputs a train of read data pulses synchronously with the clock pulse train. In a recording system on the other hand, the data extracting circuit 100 obtains the read data from a signal that has been read out from a recorder, not from the received data.
Ideally, the received data or read signal should have a completely square waveform. Actually, though, the data or signal is often received as a sine wave, rather than a square wave. This is because the waveform is possibly affected by distortion, phase noise or filtering effects resulting from inconstant state transitions over a signal path or clock jitter observed at the time of transmission. Also, the data or signal often has its eye pattern narrowed due to phase noise, for example. A QAM or QPSK system of today, in particular, has an even narrower eye pattern.
Accordingly, the data extraction technique should be developed so that received data can be latched and read out at a best timing when its eye pattern expands most. Supposing the period at which the received data is transferred is T, the best timing the eye pattern expands most is usually delayed from the instant the received data changes its level (which will be herein referred to as a xe2x80x9ctransition pointxe2x80x9d) by T/2.
FIG. 17 illustrates a schematic configuration for a known data extracting circuit. As shown in FIG. 17, a phase-locked loop (PLL) circuit 110 has been used widely as a circuit for realizing the data extraction. The PLL circuit 110 includes phase comparator 111, charging pump circuit 112, low-pass filter (LPF) 113 and voltage-controlled oscillator (VCO) 114. Clock pulses, output from the VCO 114, are provided as read clock pulses. A latch 120 latches input data synchronously with the edges of the read clock pulses and then outputs the latched data as read data. According to the currently available circuit technology, the PLL 110 accomplishes phase locking at a point in time delayed from the transition point of the input data by T/2.
In actuality, however, noise often enters the charging pump circuit 112. Thus, it is difficult to realize phase locking for the PLL 110 at the instant delayed by T/2.
Hereinafter, it will be described with reference to FIGS. 18A and 18B how the charging pump circuit 112 should and does actually operate. FIG. 18A illustrates its ideal operation that is not affected by noise, while FIG. 18B illustrates its actual operation that is affected by noise.
When the PLL circuit 110 accomplishes phase locking, the phase comparator 111 outputs two types of pulses of the same width as upper and lower pulses for the VCO 114. Accordingly, in the ideal state illustrated in FIG. 18A, the upper and lower current sources of the charging pump circuit 112 have the same current value, and the integrated value of the output currents becomes zero. As a result, no phase shift is caused once phase locking has been accomplished.
In actuality, as shown in FIG. 18B, power supply or ground noise is likely superposed and the upper and lower current sources of the charging pump circuit 112 have mutually different current values as being affected by the noise. Accordingly, even when the PLL circuit 110 accomplishes phase locking and the phase comparator 111 outputs the two types of pulses of the same width as the up- and down-pulses, the integrated value of the output currents of the charging pump circuit 112 does not become zero. As a result, the oscillation frequency of the VCO 114 deviates. That is to say, phase locking is accomplished to cancel the effects of the noise, i.e., so that the up- and down-pulses are not output synchronously but at mutually different times. This means that phase shift has been caused by the noise. In that case, the data extracting circuit cannot latch the received data at the best time, delayed from the transition point of the data by T/2, and has its performance deteriorated.
Also, the PLL is a feedback circuit. Accordingly, in extracting data, its response time is also restricted by the response time of the feedback circuit. For that reason, it is usually difficult to extract data quickly enough.
It is therefore an object of the present invention to provide a data extracting circuit that can extract data much more accurately at a much higher response speed.
Specifically, an inventive data extracting circuit includes clock transfer section, edge detecting section, clock selecting section and latch. The clock transfer section includes multiple unit delay devices connected in series together and propagates an input clock signal through the delay devices. The edge detecting section locates an edge of the clock signal and outputs an edge detection signal indicating the clock signal edge located. The edge, which is being propagated through the clock transfer section, should be found for a time represented by a given edge of an input data signal. Responsive to the edge detection signal, the clock selecting section selects one of outputs of the delay devices. And the latch receives the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and outputs read data.
According to the present invention, an edge detecting section locates an edge of an input clock signal. The edge, which is being propagated through a clock transfer section, should be found for a time represented by a given edge of an input data signal. Then, responsive to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices. And the selected output is presented as a clock input to a latch. Accordingly, the instant the data signal changes its level, the clock signal can be timed to the level transition. As a result, data can be extracted with very good responsiveness.
Another inventive data extracting circuit includes clock transfer section, edge detecting section, first and second groups of switches, selected clock transfer section, first and second data transfer sections and latch. The clock transfer section includes multiple unit delay devices connected in series together and propagates an input clock signal through the delay devices. The edge detecting section locates an edge of the clock signal and outputs an edge detection signal indicating the clock signal edge located. The edge, which is being propagated through the clock transfer section, should be found for a time represented by a given edge of an input data signal. The first group of switches are provided for the respective delay devices. Responsive to the edge detection signal, each said switch of the first group selectively delivers the output of associated one of the delay devices. The selected clock transfer section includes multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the first group. The first data transfer section also includes multiple unit transfer gates connected in series together, and propagates the input data signal through the transfer gates thereof. The second group of switches are provided for the respective transfer gates of the first data transfer section. Responsive to the edge detection signal, each said switch of the second group selects the output of associated one of the transfer gates. The second data transfer section also includes multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the second group. And the latch receives an output of the second data transfer section and an output of the selected clock transfer section as data and clock inputs, respectively, and outputs read data.
An inventive data extracting system includes data extracting circuit, PLL circuit, FIFO memory and read enabling means. The data extracting circuit may be designed according to any of the embodiments of the present invention. The PLL circuit receives the data signal, which is also input to the data extracting circuit, and generates and delivers the clock signal to the data extracting circuit. The FIFO memory receives the read data and a read clock signal, which have been output from the data extracting circuit, as its input data and input clock signal, respectively. The read enabling means monitors a phase locking state of the PLL circuit. And when the PLL circuit accomplishes the phase locking, the read enabling means delivers the clock signal, which has been generated by the PLL circuit, as an output clock signal to the FIFO memory.
Another inventive data extracting system includes data extracting circuit, quartz oscillator, FIFO memory and read enabling means. The data extracting circuit may be designed according to any of the embodiments of the present invention. The quartz oscillator generates and delivers the clock signal to the data extracting circuit. The FIFO memory receives the read data and a read clock signal, which have been output from the data extracting circuit, as its input data and input clock signal, respectively. The read enabling means counts the number of pulses of the clock signal generated by the quartz oscillator. When the count reaches a predetermined number, the read enabling means delivers the clock signal, generated by the quartz oscillator, as an output clock signal to the FIFO memory.